Micro-Electro-Mechanical Systems (MEMS) is the integration of mechanical elements, sensors, actuators, and electronics on a common silicon substrate through micro fabrication technology. While the electronics are fabricated using integrated circuit (IC) process sequences (e.g., CMOS, Bipolar, or BICMOS processes), the micromechanical components are fabricated using compatible “micromachining” processes that selectively etch away parts of the silicon wafer or add new structural layers to form the mechanical and electromechanical devices.
Poly-crystalline silicon-germanium (poly-SiGe) enables a monolithic CMOS-MEMS integration thanks to the low CMOS-compatible SiGe deposition temperatures, which are typically less than 450° C. FIG. 1 shows an example of such a MEMS-CMOS monolithic integration. Via an interconnect structure the MEMS device is electrically connected to the active devices of the CMOS substrate.
While the mechanical and electrical properties of the SiGe layer itself have been intensively studied, the electrical contact between the MEMS device and the CMOS substrate is of uttermost importance. A low resistive contact between the poly-SiGe layer and the CMOS top metal layer, typically consisting of a TiN/Al layer stack, is needed for a successful monolithic integration with low interconnect parasitic resistance.
Eyoum et al. discloses in “Low-Resistance Silicon-Germanium Contact Technology for Modular Integration of MEMS with Electronics”, Journal of Electrochemical Society, 151 (3) J21-J25 (2004), a Ni-silicide process to achieve a low contact resistance between the CMOS top metal layer and the SiGe layer. The CMOS top metal layer was modified to have a thin nickel layer on top of the TiN capping layer. During the deposition of the SiGe layer on this nickel layer the substrate is heated thereby forming a nickel germanosilicide.
The formation of a nickel germanosilicide however does require a complex and costly silicide processing. It is also a non-standard process in the CMOS backend process flow. Moreover the temperature budget of the SiGe formation must now be sufficiently high to allow forming the nickel germanosilicide, hence imposing a lower limit to the SiGe deposition temperature. In this approach the formation of the nickel germanosilicide is linked to the exact composition of the SiGe layer and the SiGe deposition conditions. From FIG. 8 of Eyoum it is clear that even for large contacts at SiGe higher deposition temperature, the contact resistance can still be above 10Ω.
The present disclosure discloses a low contact resistance between a SiGe layer and another layer such as a CMOS top metal layer or a SiGe layer.
The present disclosure discloses a low contact resistance between a SiGe layer and another layer such as a CMOS top metal layer or a SiGe layer whereby this contact resistance shows a small standard deviation.
The present disclosure discloses a low contact resistance between a SiGe layer and another layer such as a CMOS top metal layer or a SiGe layer whereby this contact resistance shows a small standard deviation and whereby the mechanical integrity of this contact is improved.
The present disclosure discloses a cost-efficient method for forming a low resistance contact between a SiGe layer and another layer such as a CMOS top metal layer or a SiGe layer.
The present disclosure discloses a cost-efficient method for forming a low resistance contact between a SiGe layer and another layer such as a CMOS top metal layer or a SiGe layer, independent of the deposition temperature of the SiGe layer(s).